Job Title: Design for Test (DFT) Engineer
Location: 100% Remote (Preferred to have local to client's HQ Sites: Vermont, Rochester MN, Raleigh, Austin & Santa Clara, but full remote OKAY if we cannot accommodate these locales)
Length: 12 months
Process: 2 rounds (1st phone screen, 2nd teams panel interview)
Start Date: Beginning of Jan but needs to identify resource NOW. Currently interviewing comp.

Scope: Client's Central Engineering ASIC Design Services team designs and develops chips for external customers in market segments ranging from artificial intelligence and machine learning to wired and wireless infrastructure, mostly in the 5G space. Client does mostly back-end design for these end clients, and they are experiencing heavy ramp-up and growth, hence the bottlenecks and needs to hire. Need to continue to complement their own full time folks with all major design disciplines (place and route, static timing analysis, physical design, etc.) but this DFT role is one of the most urgent.

They are looking for an experienced professional in the field of Design for Test (DFT) who will help with the design, analysis, and implementation of DFT structures on system-on-chip (SOC) designs to ensure successful delivery to the client.

Responsibilities:
o Develop and own the SOC test requirements and specification.
o Architect/improve the computer-aided design (CAD) DFT flow for SOCs.
o Design and implement the DFT solutions such as Scan Insertion, MBIST Insertion, Custom MBIST Pattern Generation, JTAG / IJTAG insertion, ATPG, Pattern Simulation, DFT Coverage Analysis, Scan diagnostics
o Analyze, debug, and implement fixes for reported test and DFT issues associated with the designs.
o Collaborate with global CAD teams on design flow fixes and feature improvements.

Necessary Skills:
o BS in Computer Science, Electrical Engineering or related fields, or the equivalent work experience that provides knowledge and exposure to theories, principles and concepts.
o Knowledge and over six years of experience in DFT practices and concepts, such as automatic test pattern generation, etc.
o Knowledge and over three years of experience in DFT flow and CAD tools, preferably SIEMENS (formerly MENTOR) Tessent, and experience in using them in a beginning-to-end project setting in recent semiconductor technology nodes – 5nm/7nm/10nm and 14nm/16nm are preferred but 28nm/32nm acceptable.

Preferred Qualifications:
o Thorough understanding of Linux/Unix/BSD Internals, with experience working on multi-threaded systems.
o Excellent programming skills in scripting languages (e.g., TCL, Python) in a Unix type environment, with good problem-solving skills.
o MINIMUM 6 years of prior industry experience (including co-op and internship)

Job Types: Full-time, Contract

Pay: $75.00 - $95.00 per hour

Benefits:

• 401(k)
• 401(k) matching
• Dental insurance
• Health insurance
• Vision insurance

Schedule:

• 8 hour shift
• Day shift
• Monday to Friday

Work Location: Remote

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